A NOVEL SCALABLE DEBLOCKING-FILTER ARCHITECTURE FOR H.264/AVC AND SVC VIDEO CODECS
Teresa Cervero, Andrés Otero, Sebastian Lopez, Eduardo De La Torre, Roberto Sarmiento, Teresa Riesgo, Gustavo CallicóAbstract
A highly parallel and scalable Deblocking-Filter hardware architecture for H.264/AVC and SVC video codecs is presented in this paper. The proposed architecture mainly consists on a coarse grain systolic array obtained by replicating a unique and homogeneous computational element (Functional Unit), in which an independent Deblocking-Filter unit is implemented. The proposal is also based on a novel MB-level parallelization strategy of the filtering algorithm which improves the final performance by exploiting specific data dependences, reducing by this way the communication overhead and obtaining a more intensive parallelism in comparison with the existing state-of-the-art solutions. Furthermore, the architecture is completely flexible, since the level of parallelism can be changed modifying the number of functional units working in parallel, according to the application requirements. The design has been implemented in a Virtex-5 FPGA, and it allows filtering 16CIF (1408x1152 pixels @30fps) in real-time at frequencies lower than 51Khz.
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